Crate ed25519_fast_sv_docs 

Handwritten SystemVerilog Ed25519 Fast Backend

This crate is the complete rustdoc manual for the optimized fixed-64 Ed25519 signing backend. The backend is handwritten SystemVerilog. It is compiled directly by Icarus, Verilator, and Vivado; it is not generated from RHDL. This documentation crate contains no cryptographic datapath and must not be used as evidence that the fast backend was authored in Rust or RHDL.

The active backend expands one Ed25519 seed in hardware, caches the expanded key, and signs many exactly 64-byte messages. SHA-512, scalar reduction, fixed-base multiplication, point compression, and S = r + k*a mod l all run in hardware. It does not implement verification, arbitrary message lengths, or the multipart Dalek API. Those belong to the slower RHDL compatibility track.

How to use this manual

Start with these pages in order:

1. reading_systemverilog explains the language constructs used in the RTL.
2. overview identifies the active elaboration graph and the retained legacy files.
3. signing_core follows a request through key expansion and all signing stages.
4. field, sha512, scalar, fixed_base, and point_codec document every arithmetic module, module parameter, port contract, and helper function.
5. shells_and_benchmarks documents the AXI wrapper, register map, traffic counters, and benchmark-only logic.
6. build_and_verification records the exact source lists and the distinction between simulation, OOC synthesis, routed hardware, and projections.

Active hierarchy

fast64_cached_sign_io_kernel                 optional AXI/HBM shell
`-- fast64_cached_sign_core                  cryptographic top
    |-- sha512_compress_pool                 four workers, two request ports
    |   `-- sha512_compress_3phase           80 recirculated rounds
    |-- scalar_reduce_wide_dsp_pipe x2       nonce r and challenge k
    |   `-- radix16_const_q_mul_pipe x3      fixed modulus folds
    |-- multicomb_mul_stream                 [a]B during load and [r]B per signature
    |   |-- multicomb_lookup_rom             constant-pattern table scan
    |   |   `-- multicomb_scan_bank8 x4
    |   |       `-- multicomb_scan_bank x4
    |   |-- radix51_field_mul_pipe x4
    |   `-- radix17_field_addsub_pipe x2
    |-- point_compress_pair_parallel4
    |   `-- point_compress_pair_stream x4
    |       `-- radix51_field_mul_pipe x4
    `-- scalar_muladd_dsp_pipe
        |-- radix16_wide_mul_pipe
        `-- scalar_reduce_wide_dsp_pipe

The 512 in the standard benchmark is a request count. It is not a pipeline depth. The design has 64 signing contexts, 16 point contexts, four SHA workers, eight 17-position field multipliers, two 46-position scalar digest reducers, and one 69-position scalar multiply-add pipeline. The current RTL interval is 198.509 cycles/signature; current matching-source OOC synthesis meets 200 MHz, but current source has not been placed. A predecessor was routed standalone at 199 MHz and routed unsuccessfully in the full platform, so no current xclbin or hardware throughput claim exists.

Scope and naming

Names beginning with rhdl_ed25519_fast_ are Cargo package names and directory names. They do not imply that the enclosed rtl/*.sv files were emitted by RHDL. The Rust packages provide models, black-box descriptors in limited cases, and test orchestration around the handwritten RTL.

All numeric performance and resource claims must identify both the source revision and implementation stage. A Verilator cycle interval is not a clock measurement; an OOC timing estimate is not routed timing; a previous xclbin is not hardware evidence for the current source.

Modules

build_and_verification

Source manifests, simulation entry points, synthesis scripts, and evidence rules.

field

Field addition, subtraction, and multiplication datapaths.

fixed_base

Fixed-base lookup, recoding, and signed multi-comb multiplication.

overview

Source status, elaboration hierarchy, dataflow, and build boundaries.

point_codec

Projective Edwards point compression and paired batch inversion.

reading_systemverilog

A reading guide for the SystemVerilog constructs used by the backend.

scalar

Scalar reduction, multiplication, and multiply-add datapaths.

sha512

SHA-512 compression worker and multi-worker request pool.

shells_and_benchmarks

AXI kernel, benchmark engines, register maps, and traffic behavior.

signing_core

Cached and legacy fixed-64 signing cores, including every helper function.